The present invention generally relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a serial access memory.
Generally, an image memory used in the field of image processing has two ports; a random port and a serial port. The random port is connected to a central processing unit (hereinafter simply referred to as a CPU), and the serial port is connected to a display device such as a cathode-ray tube display device. The access speed at the serial port is desired to be as fast as possible since it directly influences the image displaying speed. Particularly, there is a need to use a higher-access speed image memory as an image memory used for high-speed image processing for drawing pictures at high speeds.
Referring to FIG. 1, there is illustrated a conventional semiconductor memory device having a serial access memory. Referring to FIG. 1, a semiconductor memory device 1 includes a random access memory (hereinafter simply referred to as a RAM) 2, and a serial access memory (hereinafter simply referred to as a SAM) 3. The RAM 2 includes memory cells located at intersecting points where word lines and bit lines intersect. One of the word lines is selected by a row address supplied from an external device such as a CPU, and one of the bit lines is selected by a column address supplied therefrom. The SAM 3 is made up of an address counter 3a, a redundancy decision circuit 3b, a data register 3c, and an input/output buffer 3d. The address counter 3a inputs, as an initial address value for serial access, the column address in synchronism with a rise of a serial access strobe signal SAS, and generates a corresponding serial access address SA.sub.AD. The redundancy decision circuit 3b compares the serial access address SA.sub.AD with a predetermined redundancy address, and outputs a redundancy switching signal SOM when the compared addresses are identical to each other. The data register 3c has storage (register) cells and redundancy cells amounting to one line of the RAM 2. The storage cells are accessed one by one in series in synchronism with the redundancy address SA.sub.AD. When the redundancy switching signal SOM is supplied to the data register 3c,the redundancy cells are accessed. The serial input/output buffer 3d connects the data register 3c and an input/output terminal 4 in the bidirection.
However, the conventional device as shown in FIG. 1 presents the following disadvantages. The address counter 3a inputs the column address labelled C.sub.AD in synchronism with a rise of the serial access strobe signal SAS, as shown in FIG. 3(B). In other words, a timing with which the column address is input corresponds to the rise of the serial access strobe signal SAS. Then the address counter 3a outputs the serial access address SA.sub.AD, and then the redundancy decision circuit 3b outputs the redundancy switching signal SOM to the data register 3c. Thus, the serial access speed of the device is not so high.
It is inevitable that a large storage capacity memory device is configured so as to have a redundancy structure and therefore redundancy decision procedure is necessarily required. In the redundancy decision procedure, an address for cells requested to be accessed is compared with the redundancy address which is programmed information indicative of defective cells, and a decision is made based on whether both the addresses are the same. It is noted that the above-mentioned redundancy decision procedure cannot be done until the address of cells requested for accessing, that is, the serial access address SA.sub.AD is settled. In the above-mentioned manner, the serial access cannot be done until the serial access address SA.sub.AD is settled and then the redundancy decision procedure is executed. Even when the length of a period of the serial access strobe signal SAS is reduced in order to speed up the serial access, there is a limit on the possible length of period due to a time necessary for the settlement of the serial access address SA.sub.AD and the redundancy decision procedure. The above description holds true for an alternative in which the column address C.sub.AD is input in the address counter 3a in synchronism with a fall of the serial access strobe signal SAS.